Freeze the exact package, land pattern or die attach, RF launch, board stack, controlled-impedance geometry, ground return, via field, decoupling placement and enclosure transition. The exposed pad, flange, carrier or backside can be both the RF ground and dominant thermal path. Solder voids, long bonds, sparse vias or an altered substrate can therefore change gain, stability and temperature together.
Define copper thickness, finish, stencil, solder or conductive attach, reflow or cure, flatness, void and inspection criteria. Use manufacturer guidance as the starting boundary, then verify the actual fabrication and assembly process. If an evaluation board uses a different laminate, thickness, connector launch or heat spreader, its result must be translated by analysis and correlation rather than copied.
Calculate internal dissipated power for each bias, RF power and duty state, then combine it with the correct junction-to-case, junction-to-board or transient thermal path and a measured reference temperature. Validate case, exposed-pad, board or baseplate temperature on the intended layout. Keep margin to the device-specific junction or channel limit; thermal resistance alone is not a reliability or lifetime claim.