PLL settling time is the interval from a named event until the RF output enters and stays within the project’s frequency, phase, amplitude and spectral error limits. Lock detect usually reflects an internal phase/frequency-detector or counter condition and can assert while residual phase, level or spurs remain outside the usable window.
Define the start event, old and new frequencies, power state, reference mode, error bands, observation bandwidth, dwell time and deadline. Test the largest and smallest hops, band crossings, output-level changes, reference reacquisition and temperature extremes. If the system mutes the source, include mute release and transient leakage.
Reject a data sheet that gives only a nominal lock time without step, tolerance or measurement method. The acceptance capture should trigger from the real control command and show RF frequency or phase error and output level through the deadline; for burst, radar or hopping systems, also confirm spurs and modulation quality in the first usable interval.